In the field of semiconductor memory devices, three-dimensionally stacked memory that is capable of higher bit densities and relatively unaffected by constraints due to limits of the resolution of lithography is drawing attention. Such a three-dimensionally stacked memory includes, for example, memory strings disposed two-dimensionally in a matrix configuration, where each memory string is formed by forming a semiconductor pillar in a columnar configuration, stacking a tunneling insulating layer, a charge storage layer, and a blocking insulating layer to cover the side surface of the semiconductor pillar, and providing multiple electrode films at a prescribed spacing in the stacking direction to intersect the semiconductor pillar.
Technology has been proposed to increase the reliability of such a three-dimensionally stacked memory by using a gap (an air gap) as the tunneling insulating layer.
Also, technology has been proposed to improve the characteristics of such a three-dimensionally stacked memory by using a semiconductor pillar formed in a hollow configuration using polysilicon or amorphous silicon and by forming an insulating layer on the outer wall of the semiconductor pillar using silicon oxide or silicon nitride.
However, there is a risk that the read-out speed may decrease as the number of stacks increases and the series resistance of the NAND column increases; and it is desirable to further increase the read-out speed.